The present invention relates generally to a method of fabricating isolated islands and more specifically to a method of fabricating isolated islands for complementary bipolar transistors.
Building bipolar transistors in integrated circuits having both NPN and PNP transistors has always been a difficult task. These generally include compromises on the different steps and impurity level, usually at the expense of the PNP transistor. In junction isolated circuits, either triple diffusion steps have to be performed, or lateral structures must be used to achieve the design goals. In dielectric isolation technology, the lateral bipolar transistor structure has significant limitations because of the surface effects and other technical limitations. In vertical structures in dielectric isolation technology, it is very difficult to provide a low resistance buried layer to the PNP transistor. The importance of the buried layer is that it decreases the collector resistance and is particularly critical for high frequency devices wherein all layer thicknesses have to be very small.
Thus it is an object of the present invention to provide a new method of fabricating isolated regions for complementary bipolar transistors having thin layers.
Another object of the present invention is to provide a method of fabricating isolated complementary bipolar transistors capable of high frequency operation.
A still further object of the present invention is to provide a dielectrically isolated complementary bipolar transistor having reduced resistance buried collector portions.
An even further object is to produce isolated complementary bipolar transistors with fewer process steps, including fewer photoresist masking steps and increased mask precision.
These and other objects of the invention are attained by forming first and second buried regions of opposite conductivity type in first and second regions of a horizontally isolated substrate. The horizontal isolation may be a dielectric or junction isolation. A first mask is formed over the second region and exposing the first region, and a third region of the first conductivity type is epitaxially deposited over the first region to the thickness of the mask and having a lower impurity concentration region than the buried first region. The first mask is removed and a second mask is formed by self-aligning technique over the third region and exposing the second region. A fourth region of the second conductivity region and a lower impurity concentration region than the second buried region is formed by epitaxial deposition having a thickness equal to the third region. A dielectric isolation region is then formed at adjacent lateral portions of the third and fourth region and the first and second buried regions. The third and fourth regions form collector regions and impurities are introduced to form appropriate base and emitter regions for the complementary bipolar transistors.
The number of steps of masking is substantially reduced and the precision mask alignment is increased by using a self-alignment technique. The first mask is formed of a first oxide inhibiting layer followed by a first mask layer. The second mask is formed by removing the first mask layer, oxidizing using the first mask inhibiting layer as a mask to form a second mask layer of oxide over the third region and exposing the second region. The first oxide inhibiting mask layer is then removed. As a further enhancement, forming the second mask includes applying a second oxide inhibiting mask layer before oxidizing to cover the exposed portion of the top and side edges of the third region. Using, for example, reactive ion etching, the second oxide inhibiting layer is removed to form horizontal surfaces which include the top of the third region leaving the second oxide inhibiting layer on the lateral edges of the third region.
The formation of the dielectric isolated region includes removing adjacent portions of the third and fourth region and first and second buried region to form a trench. The exposed surfaces are then covered with an insulative layer and the trench is filled with a polycrystalline material. The trench is formed down to the horizontal isolation. The horizontal isolation may be a horizontal dielectric layer or may be a PN junction.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.